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On 3/1/2025 5:58 AM, Anton Ertl wrote:------------------------------Lawrence D'Oliveiro <ldo@nz.invalid> writes:
Would likely need some new internal operators to deal with bit-arrayMc 88K and My 66000 both have bit-vector operations.
operations and similar, with bit-ranges allowed as a pseudo-value type
(may exist in constant expressions but will not necessarily exist as an
actual value type at runtime).
Say:
val[63:32]
Has the (63:32) as a BitRange type, which then has special semantics
when used as an array index on an integer type, ...
The previous idea for bitfield extract/insert had turned into aUsing CARRY and extract + insert, one can extract a field spanning
composite BITMOV instruction that could potentially do both operations
in a single instruction (along with moving a bitfield directly between
two instructions).
Idea here is that it may do, essentially a combination of a shift and aYou want the offset (a 6-bit number) and the size (another 6-bit number)
masked bit-select, say:
Low 8 bits of immediate encode a shift in the usual format:
Signed 8-bit shift amount, negative is right shift.
High bits give a pair of bit-offsets used to compose a bit-mask.
These will MUX between the shifted value and another input value.
I am still not sure whether this would make sense in hardware, but isIn the extract case, you have the shifter before the masker
not entirely implausible to implement in the Verilog.
Would likely be a 2 or 3 cycle operation, say:I have done these in 1 cycle ...
EX1: Do a Shift and Mask Generation;
May reuse the normal SHAD unit for the shift;
Mask-Gen will be specialized logic;
EX2:
Do the MUX.
EX3:
Present MUX result as output (passed over from EX2).
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