Re: Why VAX Was the Ultimate CISC and Not RISC

On Sun, 2 Mar 2025 13:19:32 +0000, Anton Ertl wrote:

Lawrence D'Oliveiro <ldo@nz.invalid> writes:
>
MIPS used 64KB caches for the R2000?  Because they could, in 1986.
Motorola used 16KB caches for the 88000?  Obviously 64KB is not all
that necessary.  Acorn used a 4KB shared cache for ARM3?  Because it
allowed them to do it on a single chip; it still gives good benefits.

MIPS used SRAM external to the chip and sent out addresses 1 on the
high phase of the clock and 1 on the low phase of the clock and
violating the timing of the SRAM specs themselves. I was told that
later MIPS had a tester setup to sort SRAMs into those that met its
needs and those that did not.
Mc88100 was not allowed to use an interface twice per cycle (the
test guys objected) so we had to use 2 interfaces 1 for I$ 1 for
D$. We put FP on die and migrated the TLB to the Caches which
were 4-way set instead of direct mapped unified.
As to ARM's 4KB cache:: 68020 had a 256 byte cache, with a hit rate
just good enough (70%) to separate Instructions accesses from data
accesses at the pins. ARM's cache would have been big enough for
there to be unused cycles on its external interface.

My impression is that Bell was just grasping at straws to justify
their wrong choices.

Likely, but looking at it from the originating time perspective,
VAX would have lost PDP-11 compatibility if it were more RISC-
like. I put the mistakes up to hoping the other guys don't
advance the start of the art as much as what actually happened.

                      He looked at other differences (rather than the
instruction set) between the MIPS R2000 and the VAX, and if it
represented something that was not available at acceptable cost in
1977 (in particular, 64KB caches), he used it as justification for the
VAX.
>
- anton