Re: Why VAX Was the Ultimate CISC and Not RISC

EricP <ThatWouldBeTelling@thevillage.com> writes:

I found an ARM2 manual and the short answer is that the chip
drives the RAS and CAS signals to the dram directly.
The chip's clock is adjustable from 100 kHz to 10 MHz
and you match the cpu clock to your dram timing.
There is no READY line on the memory bus.
>
It does have one interesting feature that if the current address
is sequential to the prior one it skips the RAS cycle.

Yes, my memory is returning: someone explained here a while ago that
this allowed fast execution: Instructions are executed sequentially,
so as long as the row does not change, ARM get the instructions
quickly out of the DRAM.  Every data access incurs a RAS cycle, so the
architects added load/store-multiple in order to benefit from this
sequential-access optimization also for block copies and for register
spill and refill around calls.

Maybe switch from RV32GC to ARM T32 for my better-VAX time-travel
project:-) Might also help with the condition codes.

The Motorola Memory Book from 1979 shows MCM4027A 4kb*1 drams with
80 to 165 ns CAS access, 120 to 250 RAS access, 320 to 375 R/W cycle.
Similar numbers for MCM4116A 16kb*1 R/W cycle of 500 ns.
>
VAX probably used 4kb 500 ns drams.

But with the sequential-access optimization, 250ns cycles should be
possible (with waiting on changing rows).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>