Re: Why VAX Was the Ultimate CISC and Not RISC

On Fri, 7 Mar 2025 02:27:59 -0000 (UTC)
antispam@fricas.org (Waldek Hebisch) wrote:

Anton Ertl <anton@mips.complang.tuwien.ac.at> wrote:

By contrast, making good use of the complex instructions of VAX in a
compiler consumed significant resources (e.g., Figure 2 of
https://dl.acm.org/doi/pdf/10.1145/502874.502876 reports about a
factor 1.5 more code in the code generator for VAX than for
RISC-II). Compilers at the time did not use the CISCy features
much, which is one reason why the IBM 801 project and later the
Berkeley RISC and Stanford MIPS proposed replacing them with a
load/store architecture. 

 
VAX intstructions are very complex and much of that complexity
is hard to use in compilers.  But even extremaly simple compiler
can generate load-op combinations decreasing number of instructions.
Rather simple hack is enough to combine additions in address
artihmetic into addressing mode.  Also, operations with two or three
memory addresses are easy to generate from compiler.  I think
that chains of pointer dereferences in C should be not hard to
convert to indirect addressing mode.
 
I think that state of chip technology was more important.  For
example 486 has RISC-like pipeline with load-ops, but load-ops
take the same time as two separate instructions.  Similarly,
operations on memory take the same time as load-op-store.
So there were no execution time gain from combined instructions
and clearly some complication compared to load/store
architecture. 

In specific case of i486, with its small (8KB) unfied I+D cache,
you will see good gain from load+Op combining, even if going by cycle
count in the manual they are the same.
For Pentium , not necessarily so.

Main speed gain of RISC came from having
pipeline on a chip (multichip processors were pipelined,
but expensive, earlier single chip ones had no pipeline).
So load/store architecture (and no microcode) meant that
early RISC could offer good pipeline earlier.