Re: Why VAX Was the Ultimate CISC and Not RISC

In other news, got around to implementing the BITMOV logic in BGBCC and similar, and implementing support for Verilog style notation.
 So, writing things like:
   y[55:48]=x[19:12];
Is now technically possible in my C variant, and (if the BITMOV instruction is enabled) be encoded in a single instruction.
 Where:
   y[55:48]=x[19:12];
Is 1 instruction, main requirement is that the source and destination bitfield are the same width (widening will require multiple ops).
 If the instruction is not enabled, the fallback path is 4 to 6 instructions (in BJX2), or around 12 to 16 instructions for RV64G. I decided to also add support for BITMOV to the RV decoder via my jumbo- extension encodings (though, with some limitations on the 128-bit case due to it needing to fit into a 21 bit immediate).
 And:
   j=x[19:12];
Also a single instruction, or 2 or 3 in the fallback case (encoded as a shift and mask).
 

I find these operations handy when dealing with I/O devices that have bitfields. It makes it easy to test bits and compiles to an extract instruction.
inbyte = *irqport;
if (inbyte[7])
<do something>
Support for bitfield indexing (Verilog style) is in the Arpl compiler. I found there were enough differences from standard C I better call it a different name.

For a simple test:
   lj[ 7: 0]=li[31:24];
   lj[15: 8]=li[23:16];
   lj[23:16]=li[15: 8];
   lj[31:24]=li[ 7: 0];
Does seem to compile down to 4 instructions.