Re: Why VAX Was the Ultimate CISC and Not RISC

On Fri, 7 Mar 2025 21:00:09 +0000, BGB wrote:

On 3/7/2025 11:34 AM, MitchAlsup1 wrote:

On Fri, 7 Mar 2025 11:08:56 +0000, BGB wrote:
>

On 3/6/2025 10:09 PM, Lawrence D'Oliveiro wrote:

----------------

>
So, writing things like:
   y[55:48]=x[19:12];

>
2 instructions in My 66000. One extract, one insert.
>

>
1 instruction in this case...
>
The 3 sub-fields being, 36, 48, and 56.
>
The way I defined things does mean adding 1 to the high bit in the
encoding, so 63:56 would be expressed as 64:56, which nominally uses 1
more bit of range. Though, if expressed in 6 bits, the behavior I had
defined it as, effectively causes it to be modulo.

My 66000 uses the same trick, allowing both 64 and 0 to indicate
64-bits.

----------------------

>
For a simple test:
   lj[ 7: 0]=li[31:24];
   lj[15: 8]=li[23:16];
   lj[23:16]=li[15: 8];
   lj[31:24]=li[ 7: 0];
Does seem to compile down to 4 instructions.

>
1 innstruction:: BITR rd,rs1,<8>
>

>
In this particular case, there is also a SWAP.L instruction, but I was
ignoring it for sake of this example, and my compiler isn't that clever.

------------

>
Unlike Verilog, in C mode it will currently require single-bit fetch to
use a notation like x[17:17], but this is more because a person is much
more likely to type "x[17]" by accident (such as by using the wrong
variable, a missing '*', or ...).

I use <1,16> where the first is the length of the field, and the second
is the offset from bit<0>.