Sujet : Re: Why VAX Was the Ultimate CISC and Not RISC
De : robfi680 (at) *nospam* gmail.com (Robert Finch)
Groupes : comp.archDate : 08. Mar 2025, 00:40:06
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vqg04o$3p80h$1@dont-email.me>
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But, in Verilog, it is not uncommon to go well outside of the usual 64- bit limit that C typically imposes
Yes, all kinds of hardware structures use bit vectors >64. They also tend to have a reasonable upper limit as muxing from a bit vector can be expensive.
But, "32kb" in a single bit-vector should probably be enough for anyone...
>
I would be tempted to allow an 'int' (size_t?) to be used for the size.
For software bit vectors could be larger than for hardware. For example, I used a bit-pair vector to hold a ternary value representing memory pages for something called a page-allocation-map (PAM) which tracks which pages are allocated or free, and the end of an allocation. There could be a lot of pages in a large memory system. Scanning the bit-pair vector could be done mostly a word-at-a-time. Same thing could be done for disk pages.