Re: Why VAX Was the Ultimate CISC and Not RISC

On Sat, 8 Mar 2025 18:03:38 +0000, EricP wrote:

Anton Ertl wrote:

EricP <ThatWouldBeTelling@thevillage.com> writes:

Looking at the Signetics 82S100 in 1976 has max access of 50 ns, 600 mw
in a 28 pins dip.

>
The Commodore 64 used a 82S100 or compatible for various purposes,
especially for producing various chip select and RAM control signals
from the addresses produced by the CPU or the VIC (graphics chip).
Thomas Giesel wrote a very detailed report
<http://skoe.de/docs/c64-dissected/pla/c64_pla_dissected_a4ds.pdf> on
the original PLAs and their behaviour, in order to replace it
(apparently it's a chip that was failure-prone).

>
It looks like the C64's circuit design was one culprit.
Though I do remember back then hearing about failures over time with
other fuse programmable devices like PROMs.
Something about the sputter from the blown fuses.

A laser blasts a short wire so that there is no longer any connection.
Then, in use, the electrical forces cause the still present aluminum
wires to reconstruct themselves making contact and changing the state.
The blowable wire is still immersed within an oxide layer, preventing
the blown aluminum atoms from "really going anywhere" allowing small
forces to reassemble the wire.

He reports that the 82S100 generates the #CASRAM signal with a
propagation delay of 35ns in one direction and 25ns in the other, and
the #ROMH signal with a propagation delay of 25ns in both directions
(table 3.4).  I guess that the 50ns are the worst case of anything you
can do with the 82S100.

>
Yes, and it sounds like the circuit design depends on a race condition
between two logic paths to work. Big no-no.

In general, all signals that interact with the data path, must be
clocked and driven from the same edge of the data path. But even
here, designers must be careful to load each select line evenly
so that the line driving operand 1 forwarding has the same "cross
data path" delay as the line driving every other data path select
line.

He reports a current consumption of 102mA for the 82S100 (table 3.3),
which at 5V (the regular voltage at the time) is pretty close to the
600mW given in the data sheet.  The rest of the board, including
several chips with much more logic (CPU, VIC, SID (sound), 2xCIA
(I/O)) , consumed at most 770mA in his measurements; most of the rest
was NMOS, while the 82S100 was TTL.
>
- anton

>
This is not a problem with the 82S100.
Whoever designed that circuit didn't know what they were doing.
One can't use any combinatorial logic circuit and expect exact timing.
The manufacturer specs indicate a range of speeds which depend on
things like variations in power supply voltage, load, temperature.
In the case of the 82S100 it is 35 ns typical, 50 ns max.
Also these are logic chains, so each gate adds its own variations.
>
The circuit should be designed so it works across all timing variations
which is what synchronization clocks and flip flops are for.
And even then flip flops have their own timing variations.