Instruction Parcel Size

Recently started Q+2 development.
Trying to get code density closer to something like the 68k or VAX. Sounds like My66000 also has good code density using 32-bit parcels. If 32-bit parcels work well, I have thought to try 24-bit parcels.
Decided to stay away from other odd sized parcels which create addressing issues. Currently 3 sizes of instructions: 24 / 48 and 96-bit. The 96-bit instructions are usually for encoding a 64-bit immediate. The first two opcode bits determine the size. 00=24 bit, 01=48 bit, 10=96 bit, 11 (reserved)
ADD, AND, OR, EOR, CMP have 24-bit instruction forms:
iiiii-aaaaa-ttttt-ooooooo-00 <- immediate
bbbbb-aaaaa-ttttt-ooooooo-00 <- register
24-bit instruction forms allow using only the first 32 registers.
ADD, AND, OR, EOR, CMP 48-bit instruction forms:
fffffff-oooo-ccccccc-bbbbbbb-aaaaaaa-ttttttt-ooooooo-01
48-bit instruction forms support a sign control bit on the register spec, along with 64 registers.
LOAD / STORE word size have 24-bit forms
ddddd-aaaaa-ttttt-ooooooo-00
Conditional Branches (compare and branch) are 48-bit
pp-R-TTTTTTTTTTTTTTTTTTT-aaaaaa-bbbbbb-A-ffff-ooooooo-01
With load / store / basic arithmetic as 24-bit and 48-bit compare-and-branch a good portion of instructions should occupy the same or less storage space than a 32-bit ISA.
I have not written the assembler yet, so nothing to measure.