Re: An execution time puzzle

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Sujet : Re: An execution time puzzle
De : anton (at) *nospam* mips.complang.tuwien.ac.at (Anton Ertl)
Groupes : comp.arch
Date : 11. Mar 2025, 09:13:15
Autres entêtes
Organisation : Institut fuer Computersprachen, Technische Universitaet Wien
Message-ID : <2025Mar11.091315@mips.complang.tuwien.ac.at>
References : 1 2
User-Agent : xrn 10.11
Robert Finch <robfi680@gmail.com> writes:
It looks like LLVM is calculating 6 cycles (14000/2342) same as what you
would expect.

Yes, and what I see from the assembly-language variant.

Could there be something else interfering with the
performance stat (interrupts?)

I see no reasons for more than usual interference from interrupts.

Does it matter which core it is running
on? Performance or economy?

There are no efficiency cores on the Ryzen 8700G where my Zen4
measurements were taken.  But certainly the microarchitecture plays a
role, and on CPUs with cores with several microarchitectures, one sees
different results: the Golden Cove and Gracemont results in
<2025Mar10.181427@mips.complang.tuwien.ac.at> were measured on the
same CPU.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>

Date Sujet#  Auteur
10 Mar 25 * An execution time puzzle11Anton Ertl
10 Mar 25 +* Re: An execution time puzzle7Anton Ertl
10 Mar 25 i+* Re: An execution time puzzle2Brett
10 Mar 25 ii`- Re: An execution time puzzle1Anton Ertl
10 Mar 25 i`* Re: An execution time puzzle4Anton Ertl
11 Mar 25 i `* Re: An execution time puzzle3Anton Ertl
11 Mar 25 i  `* Re: An execution time puzzle2Michael S
11 Mar 25 i   `- Re: An execution time puzzle1Anton Ertl
10 Mar 25 `* Re: An execution time puzzle3Robert Finch
10 Mar 25  +- Re: An execution time puzzle1Michael S
11 Mar 25  `- Re: An execution time puzzle1Anton Ertl

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