Re: MSI interrupts

On Sat, 15 Mar 2025 2:10:48 +0000, Robert Finch wrote:

Okay, all of this MSI-X stuff is starting to percolate into my brain.
Coming up with a lighter-weight version of MSI-X for Q+. MSI-X has more
capacity than is needed for the Q+ SoC. I desire something in between
the simple and the complex. Interrupts are complex in multi-master
systems.

Interrupts should utilize a message pathway already used by other
"system things". This eliminates any cost "ON" the interrupts
themselves.
Secondly, you want to be in a position where is someone chooses Q+
as their main CPUs, that they are not hindered in building large
systems using it.

Q+ SoC has just 32-bits for the IRQ message payload data as many devices
are 32-bit and IRQ messages are passed on the 32-bit response bus. That
means a full I/O address cannot be used as it would be too large. As the
message data, the I/O device supplies the vector number (12-bits) and
interrupt controller number (6 bits). Specific interrupt controllers are
targeted rather than an I/O address as targeting requires only six bits
rather than a 32+ bit I/O address. Currently there will be only one
interrupt controller in the system. Interrupt controllers could be
designed to do other things like log to memory.

Under advice of council (EricP), I punted HW vectoring--which removed
a couple of pointers from the device:function control block along with
restrictions on where said table is, and on what alignment it is.

Each interrupt controller has a base addresses and length for the vector
tables so they may be located in system RAM (DRAM). The interrupt
controller takes care of fetching the vector and broadcasting the vector
to a specific CPU core.

There are situations where you want any 1 from a set of cores to "take"
the interrupt, rather than targeting one core (which may be busy at the
time.

                        The target CPU core is programmable in the
vector table. The vector contains 128-bits of information (almost same
format as MSI-X) and identifies the ISR address and processing core.
32-bits of data may also be supplied in the vector table entry.
>
To simplify things, the current interrupt controller contains the vector
table in BRAM in a compressed format which supports 512 vectors for each
operating mode. (2048 vectors total). The vector table is mapped into
the MMI/O space. The interrupt controller reads from its internal vector
table and directly supplies the CPU with the vector on a dedicated bus.

Those kinds of details have been punted to SW.

I had the thought of supplying an instruction to the CPU rather than an
address, ala 8080. Normally this would be a JMP instruction to the ISR.
Other instructions may be useful like task-switch or interrupt return.