Re: MSI interrupts

On Tue, 18 Mar 2025 1:34:40 +0000, Scott Lurndal wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

On Mon, 17 Mar 2025 18:33:09 +0000, EricP wrote:
>
Interrupt latency is dependent on executing instructions,
Lowest waste of power
>
But note: In most cases, it already took the interrupt ~150 nanoseconds
to arrive at the interrupt service port. 1 trip from device to DRAM
(possibly serviced by L3), 1 trip from DRAM back to device, 1 tip from
device to interrupt service port; and 4 DRAM (or L3) accesses to log
interrupt into table.

>
How do you handle timer interrupts?  Those are generally not
message based, but rather internal signals within the core that
raise an interrupt (perhaps coordinating with the interrupt controller
for priority, security state, and enable bit).  These are generally
wired (and the enables/state/priority are flops) for low latency.

Wired interrupts are converted into MSI-X interrupts under control
of INTk->MSI-X control registers in HostBridge. Then these
smell just like any other interrupt and take similar paths.

There will generally be at least one general purpose timer per
core plus any watchdog timers.

There are 8 performance counting "things" per major block on die.
major block include {core[*], L2[*], interconnect, L3[*], DRAM[*]
config[*] and MMI/O[*]}.