Re: Split instruction and immediate stream

On 2025-03-23 8:12 a.m., Marcus wrote:

Den 2025-03-23 kl. 04:06, skrev Robert Finch:

On 2025-03-22 11:04 a.m., Thomas Koenig wrote:

Marcus <m.delete@this.bitsnbites.eu> schrieb:
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Then we have the page-crossing issue. Is it better to force the
compiler/assembler to align such instructions so that they never cross
page boundaries?

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Power 10 chose to do so; actually, larger instructions cannot
cross a (likely) Cache line size there.  According to the Power
ISA Version 3.1, section 1.6:
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"Prefixed instructions do not cross 64-byte instruction address
boundaries. When a prefixed instruction crosses a 64-byte boundary,
the system alignment error handler is invoked."

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In the latest test project, the LB650 similar to a PowerPC, large constants are encoded at the end of the cache line. So, there is a similar issue of code running into the constant area.
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I have the assembler moving the code that overlaps to the next cache line.
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It is confusing to look at listing files, as there are constants output inline with the code. Makes it look like the code should not work. How does it know where to go for the next instruction? Is the question that comes to mind.
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For now, the hardware decoder takes the cheezy approach of marking instructions fetched in the constant area as invalid. The constant area gets fetched and loaded into the pipeline, but as NOPs.
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It is quite a trick getting the assembler to place constants at the end of the cache line and generate references to the constants. It is interesting because I have *constants* being relocated by the assembler / linker. Normally there would not be a relocation associated with a constant. A relocation reference to the constant is spit out by the assembler, and the linker updates the index to the constant in the code.
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It does not quite work yet. Constants are placed and code is moved, but the linked program does not have the correct references yet.
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Experimental, but looking like things will work.
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 Although I have not tried any of these techniques, here are my thoughts.
 Why not always place the constant next to (right after) the instruction
that references it, instead of at an offset within the cache line?
>

That is a very good idea. It is the same thing almost as using a variable length instruction.
LB650 uses a smaller constant packet (16-bits) than the instruction. So, instructions would need to be able to be aligned at 16-bit boundaries. LB650 instruction are fixed 32-bit. There is also the possibility of sharing the same constants, although slim.

The effect should be very similar, but now you have a simpler offset
(it's always zero) and you eliminate the problem with having to keep
track of where the constants are in order to prevent the PC/IP from
running into the constant area.
 

I wish I had thought of that last night. But I have coded things now. Got the compiler / assembler going. The listings are a few percent shorter than the PowerPC. It may be due to bugs yet. I think the difference may be the PowerPC burns up bits using pairs of instructions for high/low halves of the constant.
The vbcc compiler for the PowerPC was modified.