Software synchronization (was: Re: MSI interrupts)

In article <vsd9ak$3e0u4$1@dont-email.me>,
Robert Finch  <robfi680@gmail.com> wrote:

[Big snip]
Having some trouble following the discussion as I do not have a lot of
experience working with software threads. I know they need
synchronization means.
>
Are you talking about two different kinds of “threads”? RISCV at least
refers to ‘harts’ which I think stands for hardware threads. A CPU core
may support multiple harts, which implies multiple copies of the
processor state. In a multi-core system there could be multiple harts
even though each core is only supporting a single one. I am under the
impression hardware and software threads are not the same thing.
I hope I got the lingo correct.

Throughout this discussion, I have been using the terms
"processor", "core", and "CPU" to refer to what Intel calls a
"logical processor", which may be a core, or a thread in an SMT
configuration.  RISC-V "harts" are basically the same thing as
x86 LPs.

The way to think about this from the software perspective is
that (software) threads are a unit of logical concurrency, while
hardware threads (or cores, processors, whatever) are units of
physical parallelism.  Note that concurrency and parallelism are
two different things: one can have concurrent programs running
on a uniprocessor system.  Here, for example, is a talk from Rob
Pike where he discusses this in the context of the Go
programming language: https://go.dev/blog/waza-talk.

For a more formal treatment of the subject, consider:
https://www.cs.cmu.edu/afs/cs/academic/class/15210-f15/www/tapp.html#_parallelism_versus_concurrency
though this is a bit more approachable:
https://existentialtype.wordpress.com/2011/03/17/parallelism-is-not-concurrency/

Note, however, that concurrency is not required for pallelism,
as Leiserson notes here:
https://www.cs.cmu.edu/~guyb/spaa/2012/workshop/leiserson-talk.pdf

- Dan C.