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On 2025-03-31 4:52 p.m., MitchAlsup1 wrote:--------------------On Mon, 31 Mar 2025 18:56:32 +0000, BGB wrote:
How much of that is figuring out who to switch to and, now that that hasENTER saves as few as 1 or as many as 32 and remains that 1 single>
instruction. Same for EXIT and exit also performs the RET when LDing
R0.
>>Canary values are in addition to ENTER and EXIT not part of themGranted, the folding strategy can still do canary values, but doing so
in the reused portions would limit the range of unique canary values
(well, unless the canary magic is XOR'ed with SP or something...).
>
IMHO.
In Q+3 there are push and pop multiple instructions. I did not want to
add load and store multiple on top of that. They work great for ISRs,
but not so great for task switching code. I have the instructions
pushing or popping up to 17 registers in a group. Groups of registers
overlap by eight. The instructions can handle all 96 registers in the
machine. ENTER and EXIT are also present.
>
It is looking like the context switch code for the OS will take about
3000 clock cycles to run.
Not wanting to disable interrupts for that
long, I put a spinlock on the system’s task control block array. But I
think I have run into an issue. It is the timer ISR that switches tasks.
Since it is an ISR it pushes a subset of registers that it uses and
restores them at exit. But when exiting and switching tasks it spinlocks
on the task control block array. I am not sure this is a good thing. As
the timer IRQ is fairly high priority. If something else locked the TCB
array it would deadlock. I guess the context switching could be deferred
until the app requests some other operating system function. But then
the issue is what if the app gets stuck in an infinite loop, not calling
the OS? I suppose I could make an OS heartbeat function call a
requirement of apps. If the app does not do a heartbeat within a
reasonable time, it could be terminated.
>
Q+3 progresses rapidly. A lot of the stuff in earlier versions was
removed. The pared down version is a 32-bit machine. Expecting some
headaches because of the use of condition registers and branch
registers.
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