Re: MMU using base and bound

On 2025-04-10 12:30 p.m., Al Kossow wrote:

On 4/10/25 12:02 AM, Robert Finch wrote:

Working on the MMU component tonight.
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Just realized that it is possible to have only a single hierarchical page table in the system if base and bound addressing is applied before translating with the page table. Or to reduce the number of page tables using the base/bound addressing.
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Building base/bound registers into the MMU, pondering having multiple sets of registers to reduce the amount of register swapping. A single BRAM should be enough for 32 sets of 16 registers. Could store an index for selecting the set in the process control block. Defaulting set zero for flat addressing.
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 Congratulations, you've reinvented the SUN / CADR segment/page MMU made from two sets of SRAMS
 

It is kind of similar in concept. I tried looking it up, and found the m68k MMU. I did not give enough details of my MMU. The base/bound registers feed the TLB on a TLB miss. The TLB then feeds the paging. The registers may not be that useful, but they are also low cost. They add only about 1% to the size of the MMU.
The MMU can handle multiple outstanding misses, which it queues for the page table walker.