Re: MMU using base and bound

On 4/10/2025 12:02 AM, Robert Finch wrote:

Working on the MMU component tonight.
 Just realized that it is possible to have only a single hierarchical page table in the system if base and bound addressing is applied before translating with the page table. Or to reduce the number of page tables using the base/bound addressing.
 Building base/bound registers into the MMU, pondering having multiple sets of registers to reduce the amount of register swapping. A single BRAM should be enough for 32 sets of 16 registers. Could store an index for selecting the set in the process control block. Defaulting set zero for flat addressing.
 

Separating the protection aspects (base and bound) from the real memory management aspects (paging) has advantages and disadvantages.  Al mentioned one implementation (with which I am not familiar), but the Mill also does that (though currently at least, only in simulation/emulation) and, (out of historical compatibility requirements) the Unisys 2200 series (currently emulated but there were dedicated hardware implementations)
There is some documentation of the Mill online, and there is complete documentation of the Unisys implementation online.  Note if you start to read the Unisys documentation, they call the memory associated with a particular base and bound, a "bank"
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  - Stephen Fuld
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