Sujet : Re: virtualization, Constant Stack Canaries
De : mitchalsup (at) *nospam* aol.com (MitchAlsup1)
Groupes : comp.archDate : 17. Apr 2025, 19:22:35
Autres entêtes
Organisation : Rocksolid Light
Message-ID : <9025d11af73350f61c2f1c359a08d6c7@www.novabbs.org>
References : 1 2 3 4 5
User-Agent : Rocksolid Light
On Thu, 17 Apr 2025 1:04:10 +0000, John Levine wrote:
According to Scott Lurndal <slp53@pacbell.net>:
I think you could gain a tiny amount of efficiency if the OS (super)
allowed the user to set up handle certain classes of exceptions, e.g.
divide faults) itself rather than having to go through the super.
>
Think carefully about the security implications of user-mode interrupt
delivery. Particuarly with respect to potential impacts on other
processes running on the system, and to overall system functionality.
>
Handling interrupts requires direct access to the hardware from
user-mode.
>
I think he was talking about exceptions, not interrupts. I don't see
much danger in reflecting divide faults and supervisor calls directly
back
to the virtual machine. I gather that IBM's virtualization microcode
has done that for decades.
I used (I think) the word interrupted as in "the thread currently in
control
has its instruction stream interrupted" which could stand in for
interrupts
or exceptions or faults; to see how the conversation develops.
It seems to me that to "take" and interrupt at user layer in SW-stack,
that the 3-upper layers have to be in the same state as when that User
thread is in control of a core. But, It also seems to me that to "take"
an interrupt into Super, the 2 higher layers of SW-stack also have to
be as they were when that Super thread has control. You don't want
HV[j].GuestOS[k] to take an interrupt when Hyper != HV[j] && Super !=
GuestOS[k] -- because the various translation tables are not properly
available to perform the nested MMU VAS->UAS translation.
In effect, the SW-stack becomes some kind of "closure" where control
can be transferred asynchronously. Enough information is passed (as
arguments) across this boundary that efficient dispatch to the proper
ISR is but a few instructions (3 typically in My 66000).
External interrupts are indeed a lot harder unless you know a whole lot
about the thing that's interrupting.