Re: asynch register rename

Changed the rename logic for StarkCPU, moved it from the in-order rename stage to an asynchronous process that operates on the re-order buffer. Primary reason was instructions may need too many destination register renames, causing stalls in the pipeline. As an async process the name supplier picks off up to four destination registers per clock. Following instructions do not stall because of the name supply. Usually this would be four instructions worth, but it may be less. This is in lieu of implementing instructions with micro-ops. Instructions with multiple targets could be implemented using multiple micro-ops. For Stark many instructions have a compare-to-zero built in that requires updating a condition register in addition to the destination register update. Signified with the ‘.’ suffix in assembler. With both carry and compare-to-zero at the same time there may be three destination registers in an instruction.