Re: DMA is obsolete

On Sun, 27 Apr 2025 18:35:08 +0000, Theo wrote:

Lars Poulsen <lars@cleo.beagle-ears.com> wrote:

What is the difference between DMA and message-passing to another core
doing CMOV loop at the ISA level?
>
DMA means doing that it the micro-engine instead of at the ISA level.
Same difference.
>
What am I missing?

>
Width and specialisation.
>
You can absolutely write a DMA engine in software.  One thing that is
troublesome is that the CPU datapath might be a lot narrower than the
number
of bits you can move in a single cycle.  eg on FPGA we can't clock logic
anywhere near the DRAM clock so we end up making a very wide memory bus
that
runs at a lower clock - 512/1024/2048/...  bits wide.  You can do that
in a
regular ISA using vector registers/instructions but it adds complexity
you
don't need.

With anything at 7nm or smaller, the main core interconnect should be
1 cache line wide (512 bits = 64 bytes :: although IBM's choice of 256
byte cache lines might be troublesome for now.)

The other is that there's often some degree of marshalling that needs to
happen - reading scatter/gather lists, formatting packets the right way
for
PCIe, filling in the right header fields, etc.  It's more efficient to
do
that in hardware than it is to spend multiple instructions per packet
doing
it.  Meanwhile the DRAM bandwidth is being wasted.

SW is nadda-verrryyy guud at twiddling bits like HW is.