Re: fractional PCs

On Tue, 29 Apr 2025 2:35:27 +0000, Robert Finch wrote:

On 2025-04-28 10:06 a.m., EricP wrote:

Robert Finch wrote:

----------------

>
Exception handler needs the auxiliary info to know what to fix.
>

I may have to review my setup. I thought the exception handler would be
able to determine what is going on given the exception PC. It can find
the instruction excepting. The bad address for a page fault / privilege
violation is available in the MMU via load/store instructions. There is
nothing stored in the pipeline other than a fault cause code.

For My case: The handler arrives with causation in R0, the first 64-bits
of the instruction in R1, and up to 3 operands to that inst in R2..R4.
In the case of page fault, the generated virtual address R2, and the
faulting PTE R3 are available to the handler. If the PTE is GuestOS
pertinent, the fault is delivered to GuestOS, if the PTE is HyperVisor
pertinent, the fault is delivered to HyperVisor.

Other information needed for micro-op execution is part of the ordinary
state of the CPU. Micro-ops use several GPRs dedicated to micro-ops
usage.

Do you have a code for when the microOp wants to use the same register
as the original instruction supplied ??