Re: fractional PCs

On Wed, 30 Apr 2025 5:21:13 +0000, Robert Finch wrote:

On 2025-04-29 5:39 p.m., MitchAlsup1 wrote:

On Tue, 29 Apr 2025 2:35:27 +0000, Robert Finch wrote:
>

On 2025-04-28 10:06 a.m., EricP wrote:

Robert Finch wrote:

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Exception handler needs the auxiliary info to know what to fix.
>

I may have to review my setup. I thought the exception handler would be
able to determine what is going on given the exception PC. It can find
the instruction excepting. The bad address for a page fault / privilege
violation is available in the MMU via load/store instructions. There is
nothing stored in the pipeline other than a fault cause code.

>
For My case: The handler arrives with causation in R0, the first 64-bits
of the instruction in R1, and up to 3 operands to that inst in R2..R4.
In the case of page fault, the generated virtual address R2, and the
faulting PTE R3 are available to the handler. If the PTE is GuestOS
pertinent, the fault is delivered to GuestOS, if the PTE is HyperVisor
pertinent, the fault is delivered to HyperVisor.
>

Other information needed for micro-op execution is part of the ordinary
state of the CPU. Micro-ops use several GPRs dedicated to micro-ops
usage.

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Do you have a code for when the microOp wants to use the same register
as the original instruction supplied ??

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*poof* I forgot to take the operating mode into consideration. I think
this is easily fixed though.
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Micro-ops use a subset of the regular ISA instructions, but the register
specs fields are expanded to seven-bits so any register may be selected
for use. To use the same register as what is in the original instruction
it is just a matter of setting the extra register spec bits
appropriately. Extra bits "00" gets access to the integer GPRs. The
registers dedicated to micro-ops have codes outside of this range.
>
When I first heard about micro-ops I envisioned them as being smaller
than the instructions in the ISA because of the term "micro". For
instance 16 or even 12-bits. I was having a heck of time trying to
implement with 16-bit micro-ops. Then I clued in, why not just make them
bigger? They're not really micro-ops, it is more like mega-ops.
>
Current micro-op structure:
>
typedef struct packed {
logic v; // valid bit
logic [2:0] count; // number of micro-ops for instruction
logic [2:0] num; // the micro-op of the instruction
logic [1:0] xRs2; // extended register selection bits
logic [1:0] xRs1;
logic [1:0] xRd;
logic [3:0] xop4;
instruction_t ins; // The instruction
} micro_op_t;

That is about right at ~48-bits:: you have to be able to encode
EVERYTHING you want to do.