Re: fractional PCs

On 2025-04-30 2:09 p.m., Thomas Koenig wrote:

Robert Finch <robfi680@gmail.com> schrieb:
 

When I first heard about micro-ops I envisioned them as being smaller
than the instructions in the ISA because of the term "micro". For
instance 16 or even 12-bits. I was having a heck of time trying to
implement with 16-bit micro-ops. Then I clued in, why not just make them
bigger? They're not really micro-ops, it is more like mega-ops.

 AMD uses 64-bit micro-ops, see the link I posted recently (and
again, below).  It is actually a RISC-like ISA, which makes sense,
because you don't want to spend a lot of time decoding micro-ops.
They have 64 bit micro-op length, and most fields they could have
in any instruction has its unique place.
 https://bughunters.google.com/blog/5424842357473280/zen-and-the-art-of-microcode-hacking
 

>
Current micro-op structure:
>
typedef struct packed {
logic v; // valid bit
logic [2:0] count; // number of micro-ops for instruction
logic [2:0] num; // the micro-op of the instruction
logic [1:0] xRs2; // extended register selection bits
logic [1:0] xRs1;
logic [1:0] xRd;
logic [3:0] xop4;
instruction_t ins; // The instruction
} micro_op_t;

 Hmm... I don't know what your ISA looks like, but having the
original instruction looks strange.  Why not take a page from
AMD's book?  It looks like a reasonable philosophy, and obviously it
works for them, or they would have done something different by now.

I skimmed over the link, it is a good read. I have the micro-code / microop component placement somewhat different. All instructions going into the decode stage are converted to micro-ops. There is no cache. There is a queue. The micro-code is not connected to the micro-ops, instead it is regular instructions feeding the decoder. I may find out it is too slow. Still developing it.
I noticed they have marker micro-ops to indicate the end of the sequence. I use a a count field to calculate the micro-op span. The first micro-ops count is non-zero, subsequent micro-ops have a count of zero. That way it is possible to tell where the sequence starts.
The ISA is RISC-like with a few CISC features. The ins field it not exactly the original instruction, but rather a mutated form of it. The original instruction may be copied to this field, or an additional instruction may be placed in it.
95% of the micro-ops are for adding a compare-to-zero instruction after the ISA instruction; it implements the dot added to the mnemonic meaning update the condition reg.
ADD. R1,R2,R3
Gets translated (fissioned) to
ADD R1,R2,R3
CMP CR0,R1,R0
I have add with carry implemented like:
ADD Rd,Rs1,carry_reg
ADD Rd,Rd,<source 2> // source 2 copied from original instruction
Still working on it.