Re: OoO execution (was: The Seymour Cray Era of Supercomputers)

Michael S <already5chosen@yahoo.com> writes:

On Tue, 20 May 2025 21:21:07 GMT
anton@mips.complang.tuwien.ac.at (Anton Ertl) wrote:
>

Michael S <already5chosen@yahoo.com> writes:

[PPC604]

Yes.  The OoO nature with ROB is explained in
<https://arstechnica.com/articles/paedia/cpu/ppc-1.ars/6>.
=20
Somehow that did not register with me earlier (even though a collegue
had a Mac with a PPC 604e IIRC).  I guess it's because Apple Marketing
is low on technical details, and if Motorola emphasized this aspect,
that did not pass the filters of the press.  Also, IIRC the
performance was not so exceptional that it would direct a spotlight at
the underlying technology, whereas the Pentium Pro with its suprising
SPECint win certainly did.  Finally, the successors of the 604 (in
particular, the PPC 7450) did not progress much further with OoO
execution=20

>
=46rom uArch perspective, PPC/MPC 7xx and 7xxx are really successors of
603 rather than of 604.

Looking at <https://arstechnica.com/features/2004/08/ppc-1/>, the 603e
is also a full-blown OoO CPU (it does not describe the 603 in enough
detail to establish that for the 603);
<https://en.wikipedia.org/wiki/PowerPC_600#PowerPC_603> says that the
603 is OoO, but does not give details.  In any case, the 603 appeared
around the same time as the 604, so the 604 might be the first
full-blown OoO CPU even if the 603 also is OoO.

In any case, the 750 and 7450 are full-blown OoO machines, but still
with relatibvely small buffers: the 7450 (introduced 2001) has a
six-entry integer queue, and apparently only three of the entries can
be used for reordering (chipsnchees calls this a three-entry scheduler
preceded by a three-entry non-scheduling queue); similarly, the vector
side has a two-entry scheduler preceded by a two-entry non-scheduling
queue.  I don't find information about the size of the reorder buffer
of the 7450, but it has 16 rename registers for the GPRs and 16 rename
registers for the vector registers, which is indicative of its
reordering capabilities.

By contrast, the AMD K7 (1999) has a 15-entry integer scheduler, a
36-entry FP scheduler, a 72-entry ROB, 88 FP registers (-8 for the 8
architectural 387 registers), and IIRC 72 integer registers (-8 for
the 8 architectural GPRs).  I wonder why they needed 80 FP rename
registers if they could reorder only across 72 instructions.  In any
case, this appeared earlier and had much more reordering capability
than the PPC 7450.  I wonder why the 7450 designers chose to have that
little reorder capacity.  Too much space spent on Altivec?  Did they
have a design that was hard to scale for more entries?  Power
consumption?

An offspring that attempted to re-enter PC processors market was PPC970
(a red-headed little brother of POWER4). This foray was terminated by
Steve Jobs (he always prefer Intel but until this millennium did not
poses political power to impose his preferences on technical team)
lasting for about 3 years.

The PPC970 was marketed by Steve Jobs, as usual, as the best thing
since sliced bread, but in my work, it was slower than comtemporary
IA-32 and AMD64 systems:

All the numbers below are execution times in seconds, so lower means
faster:

From <https://www.complang.tuwien.ac.at/franz/latex-bench>

- PowerMac G5, 2000MHz PPC970, Gentoo Linux PPC64   1.47
- Athlon 64 3200+, 2000MHz, 1MB L2, Fedora Core 1 (64-bit)        0.76

From <https://cgit.git.savannah.gnu.org/cgit/gforth.git/plain/Benchres>

sieve bubble matrix  fib
0.279 0.411  0.183 0.519 0.7.0; PPC970 2GHz (PowerMac G5); gcc-4.1.2 20061115 (prerelease) (Debian 4.1.1-21)
0.245 0.287  0.156 0.376 0.7.0; Pentium 4 Northwood 2.26GHz; gcc-2.95.4 20011002 (Debian prerelease)
0.216 0.268  0.112 0.340 0.7.0; K8 2GHz (Opteron 270); gcc-4.1.3 20080623 (prerelease) (Debian 4.1.2-23)

Many years later I did some microbenchmarking
<https://www.complang.tuwien.ac.at/anton/undefined-div-bench/> that
involved division instructions.  I was surprised by the slowness of
the PPC970 on this microbenchmark.  Results in cycles per iteration
(lower is better):

  ooomb   oooub
   41.9    41.9 PPC 7447A (iBook G4) ppc (32-bit) gcc-4.3.2
  130.0   130.0 PPC 970 (PowerMac G5) ppc64  gcc-4.4.5

(but note that this compares 32-bit with 64-bit division).

As for the question of why Apple switched to Intel, it appeared pretty
clear to me: At the level where they were working, the M of AIM could
not keep up in the GHz race, the I in AIM finally manage to get the
GHz (that the performance was subpar did not register with me at the
time; Apple marketing worked:-) with the PPC970, but that was too
power-hungry for laptops.  Probably both M and I demanded more money
from A in order to develop in the direction that A was asking them to.
A did not want to provide the money, so they developed for their
specific markets: M developed what the embedded market asked for, I
developed for servers and workstations.  My guess is that Intel
already had the high-performance laptop CPUs that Apple needed,
because that was in their market, so they could offer Apple a better
deal, and that's how it went.

The irony is that P.A. Semi worked on the kind of CPUs that Apple
wanted, lost their prospective customer with this move by Apple, was
then bought by Apple in 2008, and their workforce became part of what
is now Apple Silicon, and worked on the chips that first powered
iPhones and later displaced Intel from Apple's laptop and desktop
computers.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>