Sujet : Re: Why I've Dropped In
De : anton (at) *nospam* mips.complang.tuwien.ac.at (Anton Ertl)
Groupes : comp.archDate : 11. Jun 2025, 17:51:29
Autres entêtes
Organisation : Institut fuer Computersprachen, Technische Universitaet Wien
Message-ID : <2025Jun11.185129@mips.complang.tuwien.ac.at>
References : 1 2 3 4 5 6
User-Agent : xrn 10.11
BGB <
cr88192@gmail.com> writes:
For example, SPRs can be, by definition,
not the same as GPRs. Say, if you have an SP or LR, almost by
definition, you will not be using it as a GPR.
>
So, if ZR/LR/SP/GP are "not GPR", this is fine.
I assume you mean Zero register, link register, stack pointer, global
pointer. On most register architectures (those with GPRs) all of them
are addressed as GPRs in most instructions. Specifically:
Zero register: The CISCs (S/360, PDP-11, VAX, IA-32, AMD64) don't have
a zero register, but use immediate 0 instead. Most RISCs have a
register (register 0 or 31) that is addressed like a GPR, but really
is a special-purpose register: It reads as 0 and writing to it has no
effect. Power has some instructions that treat register 0 as zero
register and others that treat it as GPR.
Link register: On some architectures there is a register that is a GPR
as far as most instructions are concerned. But the call instruction
with immediate (relative) target uses that register as implicit target
for the return address. MIPS is an example of that. Power has LR as
a special-purpose register.
Stack pointer: That's just software-defined on many register
architectures, i.e., one could change the ABI to use a different stack
pointer, and the resulting code would have the same size and speed.
An interesting case is RISC-V. In RV64G it's just software-defined,
but the C (compressed) extension defines some instructions that
provide smaller instructions for a specific assignment of SP to the
GPRs; I expect that similar things happen for other compressed
instruction set extensions.
Global pointer: That's just software-defined on all register
architectures I am aware of.
Program Counter: Some instruction sets (ARM A32, IIRC PDP-11 and VAX)
have the PC addressed like a GPR, although it clearly is a
special-purpose register. Most RISCs don't have this, and don't even
have a PC-relative addressing mode or somesuch. Instead, they use
ABIs where global pointers play a big role.
- anton
-- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>