Re: Why I've Dropped In

quadibloc <quadibloc@gmail.com> writes:

However, if the memory reference instructions had 5 bits for the
destination register, 5 bits for the index register, 5 bits for the base
register, and 16 bits for the displacement, then there would only be one
bit left for the opcode.

The solution of RISC architectures has been to not have displacement
and index registers at the same time (MIPS and its descendants do not
have base+index addressing at all).  The solution of CISC
architectures has been to allow bigger instructions, and possibly
different displacement sizes (e.g., 8 bits and 32 bits for IA-32 and
AMD64).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>