Re: Why I've Dropped In

I thought I saw a post in this thread which asked why I included VLIW
capabilities in my ISA.
Perhaps that post was deleted, or I saw it in another thread and
misremembered.
However, I thought it was worth a reply, in case anyone had forgotten
what VLIW was "good for".
Today's microprocessors achieve considerably improved performance
through the use of Out-of-Order Execution. Compare the 486, which
doesn't have it, to the Pentium II, which does have it. Intel's Atom
processors originally did not have OoO in order to be small and
inexpensive, but their low performance, and smaller transistors making
more complex chips more easily possible led to even the Atom going OoO.
OoO comes with a cost, though. It increases transistor costs
considerably. Also, it comes with vulnerabilities like Spectre and
Meltdown.
VLIW, in the sense of the Itanium or the TMS 320C6000, offers the
promise of achieving OoO level performance without the costs of OoO.
This is because it lets the pipeline achieve high efficiency by directly
indicating within the code itself when succeeding instructions may be
executed in parallel, without requiring the computer to make the effort
of determining when this is possible.
The TMS 320C6000 works by including, in each of its 16-bit instructions,
a first bit which indicates if an instruction may or may not be executed
in parallel with those which precede it.
In Concertina II, my goal was to permit a variety of implementations. A
plain one like the 486, or a large one with OoO execution, or a medium
one that has VLIW style features. To do this, I use a block structure
with block headers.
Instead of putting a bit to indicate parallelism in every instruction,
such a bit can _optionally_ be added to every instruction by beginning
each block with the appropriate type of block header.
Thus, the ISA can provide increased performance at lower cost through
use of the VLIW technique, but it's also suited to implementations which
don't use VLIW.
John Savard