Re: Why I've Dropped In

On Thu, 12 Jun 2025 8:38:06 +0000, Anton Ertl wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

On Wed, 11 Jun 2025 22:00:33 +0000, EricP wrote:
>

MitchAlsup1 wrote:

On Wed, 11 Jun 2025 16:51:29 +0000, Anton Ertl wrote:
>

Program Counter: Some instruction sets (ARM A32, IIRC PDP-11 and VAX)
have the PC addressed like a GPR, although it clearly is a
special-purpose register.  Most RISCs don't have this, and don't even
have a PC-relative addressing mode or somesuch.  Instead, they use
ABIs where global pointers play a big role.

>
I consider IP as a GPR a mistake--I think the PDP-11 and VAX
people figured this out as Alpha did not repeat this mistake.
Maybe in a 16-bit machine it makes some sense but once you have
8-wide fetch-decode-execute it no longer does.

>
Actually, it seems to me that for the first RISC generation, it made
the least sense.  You could not afford the transistors to do special
handling of the PC.

Instead, you built the increment loop around the IP itself. Basically,
you have a 4-input multiplexer, 1 leg feeds the current IP back to the
adder which is then flopped in the IP register, the other 3 inputs are
for branch displacement, interrupt vector, and JMUP register input.
It is basically a degenerate ALUU+forwarding path.

Nowadays, you can afford it, but the question still is whether it is
cost-effective.  Looking at recent architectures, none has PC
addressable like a GPR, so no, it does not look to be cost-effective
to have the PC addressable like a GPR.  AMD64 and ARM A64 have
PC-relative addressing modes, while RISC-V does not.

Consider that in a 8-wide machine, IP gets added to 8 times per cycle,
whereas no GPR has a property anything like that.

On the con side, for all PC-relative addressing the offset is
relative to the incremented PC after *each* operand specifier.
So two PC-rel references to the same location within a single
instruction will have different offsets.

>
This is exactly what made wide VAXs so hard to pipeline.

>
I don't think that would cause a real problem for decoder designers
these days.  It might cost some additional transistors, though.

I disagree, the way VLE is implemented in My 66000 allows instruction
boundary determination to be tree-ifide. The way VAX (and PDP-11) did
it does not allow tree-ififcation. My 66000 is quadratic whereas VAX
is higher than cubic when you consider the large operand instructions.
If you don't do the wide operand instructions, VAX is only a little
harder than cubic.

                                                                 This
design choice in VAX was very likely due to the implementation choices
(sequential decoding of instruction parts) they had in mind, and these
days one would probably make a different choice even if one decided to
design an otherwise VAX-style instruction set.  How did the NS32k
designers choose in this respect?
>
That being said, how does the design choice to include PC-relative
addressing in AMD64 and ARM A64 come out in the long run?  When AMD64
and ARM A64 was designed, the data was still delivered in the
microinstruction in most microarchitectures, and in that context,
PC-relative addressing does not cost extra; you just fill in the data
from the start.

My 66000 also has this property, but also the property that any IP
needed as an operand to any instruction is the virtual address of
the instruction itself (not incremented); and is thus easy to synthesize
in the DECODE pipeline.

But Intel switched to having separate rename registers in Sandy Bridge
(around the time when ARM A64) appeared, and others did the same, so
now there is no space in the microinstructions for including the value
of the PC when the instruction was decoded.

K9 was going to unify x86+64, x87, MMX-SBVE into a single register file,
too. These are decisions based on how the microarchitecture takes place.
In K9's case, the unified file was 1/2 the size of the 3 separate files.

                                             I guess that this value
is stored in a physical register on decoding, and each use of
PC-relative addressing reduces the amount of available physical
registers from the time when the register renamer processes the
instruction until the time when the instruction is processed by the
ROB; can someone confirm this, or is it done in some other way?
>
- anton