Re: Why I've Dropped In

mitchalsup@aol.com (MitchAlsup1) writes:

On Thu, 12 Jun 2025 8:38:06 +0000, Anton Ertl wrote:

[program counter as GPR]

Nowadays, you can afford it, but the question still is whether it is
cost-effective.  Looking at recent architectures, none has PC
addressable like a GPR, so no, it does not look to be cost-effective
to have the PC addressable like a GPR.  AMD64 and ARM A64 have
PC-relative addressing modes, while RISC-V does not.

>
Consider that in a 8-wide machine, IP gets added to 8 times per cycle,
whereas no GPR has a property anything like that.

Actually the 6-wide renamer of Golden Cove (Alder Lake P-core) can
handle 6 dependent adds of small constants to GPRs per cycle, and I
would be surprised if the 8-wide Lion Cove (Arrow Lake P-Core) would
not be able to do 8 dependent adds of small constants to GPRs.

However, in the case of the PC, I think you can produce the 8 PC
values with less effort.  The decoder knows where each instruction has
started, so it just needs to propagate this information as the
instruction-specific PC value to the execution-engine.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>