Re: Why I've Dropped In

On Wed, 11 Jun 2025 9:42:47 +0000, BGB wrote:

Ideally, one has an ISA where nearly all registers are the same:
   No distinction between base/index/data registers;
   No distinction between integer and floating point registers;
   No distinction between general registers and SIMD registers;
   ...

In my original Concertina design, I broke even the first rule. Index and
integer data registers were in one register bank, but the base registers
were in another.
This rectified what I thought was a mistake in the 68000, of putting
index and base registers in the Address register bank with the integer
GPRs another bank. Putting the base registers, because they were static,
in another register bank made sense, but indexes are computed.
In Concertina II, I put base and index registers in the 32 general
registers, but I still sin grievously; to fit instructions into 32 bits,
I limit index registers (in normal 32 bit instructions; there's also a
48 bit instruction without that restriction) to the first eight
registers (with 0 not used), and the base register field is also three
bits long.
The last seven registers are base registers for use with 16-bit
displacements.
Register 24 is instead a base register used for 15-bit displacements in
my homage to the System/360 Model 30.
Registers 17 through 23 are base registers for use with 12-bit
displacements. So I can have additional smaller memory regions for
things like sharing data between modules.
Registers 9 through 15 are base registers for use with 20-bit
displacements, since IBM thought 20-bit displacements were a good idea
for 64-bit computing in their z/Architecture.
As for the second rule - since instructions operate on fixed or floating
operands, having two separate register banks for fixed and floating
doubles the number of registers available without having to make the
register fields in the instructions longer. So putting floating operands
in the integer registers is something I simply had not considered.
That is, unless you consider my Simple Floating type. That uses a pair
of integer registers, putting the exponent in the first one, inspired by
the Recomp II which could handle numbers that went around the Earth 2
1/2 times.
And the third rule - hey, wait a moment, I though pairing was supposed
to be a bad idea!
So of course I have a separate bank of SIMD registers too.
Sixteen SIMD registers, each 256 bits in length. And they're a fixed
part of the architecture. No legacy MMX or AVX-128 to contend with, and
no hope of advancing to AVX-512. Instead, the 256-bit size of SIMD
vectors is a fixed and permanent part of the architectural spec.
That particular combination was chosen so that the entire SIMD register
bank could also be used as a bit matrix for 64-bit bit transpose
operations.
And I have put them to another use as well.
I reproduce IBM's memory-to-memory string operations. But doing string
operations memory-to-memory was a mistake from the perspective of today,
where memory is extremely slow compared to the CPU.
So I also use the SIMD register bank to provide string registers.
According to an old Data General Nova brochure, if you want to enter the
modern world of general register computing, the least number of
registers you need, which is also fully adequate, is four. Which happens
to be the number that their computer had.
And so I have chosen to divide the SIMD register bank into four string
registers, made up of SIMD registers 0-3, 4-7, and so on. Not two. Which
means the string registers are only 128 bytes long.
But I felt that this was OK, since as everybody knows, strings really
only have to be able to be at least 80 characters long. Hmm... wait a
moment, aren't 132-character strings sometimes needed? Oh, well.
John Savard