Re: Scan chains

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Sujet : Re: Scan chains
De : mitchalsup (at) *nospam* aol.com (MitchAlsup1)
Groupes : comp.arch
Date : 15. Jul 2025, 18:21:42
Autres entêtes
Organisation : Rocksolid Light
Message-ID : <569ef8256e4835fd163bf05b54410de7@www.novabbs.org>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
User-Agent : Rocksolid Light
On Wed, 7 May 2025 3:12:08 +0000, Stefan Monnier wrote:

Even state-of-the-art CPUs today commonly use scan-chains (via JTAG)
for debuggin.
Is there some blog somewhere that explains how scan-chains work (not
how they're used, but how they're implemented inside the CPU)?
Intuitively they sound very costly to me, because of things like the
need to run extra wires all over the place.  I'm obviously
missing something.
Actually, you're not far off.  It's a serial shift chain which is
shifted
one-bit at a time to capture flop states.  Each chain is a single wire;
a chip may have a few dozen individual shift chains.
https://www.design-reuse.com/articles/48331/scan-chains-pnr-outlook.html
>
Thanks.  Wow.  So it is really that bad, huh?
I also liked the note about speed limits and power consumption, how
shifting a state (in or out) causes (almost) all the flip-flops to
change state at each cycle, thus leading to very high power consumption.
At a very slow clock rate, and without logic burning power.

What's the approximate cost of those scan chains.  I.e. if we were to
take an existing working design and replace all the "flip-flop with
scan-chain" with "plain flip-flops", how much smaller would the
resulting chip be, how much faster could it run, and how much less power
could it consume?
A D-flip-flop can be implemented in 4 gates (but often 5)
A full scan D-flip flop is implemented in 10 gates.

I assume the cost in terms of power consumption is small because in
normal use, the scan-chain part stays completely stable so that barring
leakage it should not consume any power, save for the indirect costs
like the need to move the other bits over greater distances when
the extra wires of the scan chains get in the way.
In normal use, the scan attachments are just additional capacitance
internal to the flip-flop. In scan use, the normal outputs of the
Flip-Flops remain stable--preventing downstream logic from toggling.
Once the scan is done, and the normal clock starts again, the scan
data is gated to the flip-flop data.
>
>
        Stefan

Date Sujet#  Auteur
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31 Oct 24 +- Re: Page fetching cache controller1MitchAlsup1
6 Nov 24 `* Re: Q+ Fibonacci57Robert Finch
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18 Apr 25   ii `* Re: register sets44MitchAlsup1
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23 Apr 25   ii         +* Re: auto predicating branches3Stefan Monnier
23 Apr 25   ii         i`* Re: auto predicating branches2Anton Ertl
25 Apr 25   ii         i `- Re: auto predicating branches1MitchAlsup1
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6 May 25   ii               i    +* Re: control co-processor3MitchAlsup1
7 May 25   ii               i    i+- Re: control co-processor1MitchAlsup1
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7 May 25   ii               i    `* Scan chains (was: control co-processor)7Stefan Monnier
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7 May 25   ii               i     i`- Re: Scan chains1Stefan Monnier
7 May 25   ii               i     +* Re: Scan chains3MitchAlsup1
7 May 25   ii               i     i`* Re: Scan chains2Stefan Monnier
8 May 25   ii               i     i `- Re: Scan chains1MitchAlsup1
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