Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers

On 8/1/2024 12:17 PM, Buzz McCool wrote:

On 7/21/2024 9:16 AM, Nioclás Pól Caileán de Ghloucester wrote:

I found that the overwhelming majority of the Internet's solution to slowing down a fast clock (for making the pulsing of an LED visible to the human eye) was either using vendor-specific, proprietary clock managers and PLLs or implementing some twenty-something-bit-wide counter as to count hundreds of thousands of clock cycles and generate a 1 Hz output.

That depends on what you want to use to "trigger" the LED's illumination.
Monostables (in many forms) can generate an interval that is "close enough
for the purposes of human perception" with very little (if ANY!) silicon.

If you did not have access to FPGA shift register primitives, what would be the most efficient way to build a prescaler from discrete parts?

How do you define "efficient"?
Shift counters are incredibly simple with the drawback of front-loading
all of the combinatorial logic.  Certain divisors are, thus, more costly
than others.
Binary ripple counters use the least resources but suffer from
propagation delays making decoding of states a bit trickier.
You will always need at least log2N flip-flops and could end up
using slightly more.