Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers

On 8/1/2024, Buzz McCool wrote:

On 7/21/2024 9:16 AM, Nioclás Pól Caileán de Ghloucester wrote:

I found that the overwhelming majority of the Internet's solution to slowing down a fast clock (for making the pulsing of an LED visible to the human eye) was either using vendor-specific, proprietary clock managers and PLLs or implementing some twenty-something-bit-wide counter as to count hundreds of thousands of clock cycles and generate a 1 Hz output.

 If you did not have access to FPGA shift register primitives, what would be the most efficient way to build a prescaler from discrete parts?
 

Truthfully, the efficiency in question is rather minuscule to begin with; in a design where you have tens or hundreds of thousands of flip-flops and LUTs, attempting to optimize a prescaler to use less flip-flops might not be worth it.  However, you could still use clock managers and PLLs, because they've been dedicated for exactly that task, although that would still require you to directly instantiate (as opposed to infere) the primitives.  Ultimately, using a simple counter with as few bits as possible remains the simplest and most common method.
I wasn't actually expecting this Usenet thread to gain views after Google shut down its client, but this indeed was a pleasant surprise.