Sujet : CERN FPGA meeting
De : Spamassassin (at) *nospam* irrt.De (Niocláisín Cóilín de Ghlostéir)
Groupes : comp.lang.vhdl comp.arch.embedded comp.arch.fpga comp.lang.verilog comp.cad.synthesisDate : 28. May 2025, 10:47:25
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <0801a14c-2295-00d3-a28f-19b88abebe3e@insomnia247.nl>
I love this sentence: "You don't have time to not do good things." says Jim Lewis at circ 21:54 in
https://CDS.CERN.CH/record/2932949I am glad that the SystemC(R) percentages on Slide 5 / Page 3 are still small bt the 2024 SystemC(R) percentage is disturbingly high! Cf.
"Why Your Team Should be Using VHDL + OSVVM for Verification" by Jim Lewis. Thanks to Jim for not parroting off about object orientation on Slide 10 / Page 5. "Aspects of a Test Sequencer
* Whole test in one file" says Slide 18 / Page 9: even the Gang of Four confesses that scattering polymorphic methods throughout makes OOP code hard to comprehend. I am glad to note that other VHDL presentations are hyperlinked to from
https://Indico.CERN.CH/event/1467417/timetable/?view=standard
CERN FPGA meeting