Re: DDS question: why sine lookup?

On Tue, 6 May 2025 21:00:33 +0200, Jeroen Belleman
<jeroen@nospam.please> wrote:

On 5/6/25 17:48, john larkin wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.
 
But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?
 
The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we'll average a
lot of steps and forget the big sawtooth reset. [...]

>
Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won't have a zero response
for all possible frequencies.

Sure, the point of DDS is to generate a high-resolution (and low
jitter) clock.

>
Second, the usual reconstruction filters do *not* interpolate
into straight lines.

Seems to me that what we want the filter to do is make the
best-possible-fit  straight line, a linear ramp, out of the sawtooth
made from nasty DAC steps. But we need to ignore the giant sharp edge
of the sawtooth, which would cause a bunch of jitter. So the impulse
response of the filter has to go to zero after, say, 3/4 of the
sawtooth time, to forget that big jump.

>
Beyond that, I would have to think this over a bit more.
>
Jeroen Belleman
>
>

I'm thinking in time domain about making a low-jitter DDS clock. There
are a zillion papers that analyze this in the frequency domain.

We've sold a lot of these

https://highlandtechnology.com/Product/V375

but it's old and it's hard to find parts. It uses four expensive
parallel-input ADI DDS chips to make the clocks. I was thinking about
making my own DDS with an FPGA and some home-made DACs.

I don't need RF spectral purity. I'm simulating rotating machines, so
nobody will notice a couple nanoseconds of jitter.