Re: DDS question: why sine lookup?

On Tue, 6 May 2025 21:27:35 +0200, Gerhard Hoffmann <dk4xp@arcor.de>
wrote:

Am 06.05.25 um 17:48 schrieb john larkin:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.
 
But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?
 
The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we'll average a
lot of steps and forget the big sawtooth reset.
 
I want to make four programmable clocks and don't want to buy DDS
chips. So use a cheap FPGA and a few resistors as the DAC. Synthesize
one octave and divide down for lower frequencies. Gotta sim that.
 
LT Spice really sucks with digital stuff. Building a phase accumulator
would be a horror. I'm working on a PowerBasic program that can dump
waveforms to a PWL file that LT Spice can import and filter. Qspice
would be better but I'd have to learn that and hack the phase
accumulator in c.

>
Spice was made for solving systems of differential equations with
some semantic sugar added, but it was never intended as a digital
simulator. Yes, you can abuse it but the simulation drowns in
details that no one is interested in. The right tools would be
Modelsim/Questasim/GHDL or
<  https://en.wikipedia.org/wiki/List_of_HDL_simulators    >
>
I did publish a DDS in VHDL. It's on opencores.org under arithmetic
named sincos.
The number of pipeline stages, log table dimensions etc can be
set at will; bus sizes auto-adjust to the busses that are attached.
Mirroring of the sine table is also automatic. sin and cos are
available at the same time without requiring more hardware.
>
The only thing that's missing is Sunderland's lookup table
optimization that decomposes the ROM into two and gets a
10...50 times reduction in ROM size. I did not need it
and its added delay was not welcome in my PLL application.
>
<
https://www.researchgate.net/publication/220236321_An_Improved_Linear_Difference_Method_with_High_ROM_Compression_Ratio_in_Direct_Digital_Frequency_Synthesizer

Even better is no sinewave lookup!

    >
>
On a Spartan 6 eval board it runs at 200 MHz out of the box.

I'm thinking that I could run at 80 MHz and generate an octave from 10
to 20. It would be great to clock at 160 MHz. I probably have to clock
at a multiple of 40 for strict backward compatibility to the old
product.

>
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Cheers, Gerhard
>
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But after the DDS math we still need a DAC and an analog lowpass
filter and a comparator and some jitter analysis, which are Spice
territory.

Looks like a plain vanilla Bessel filter would be good to smooth an
ugly stepwise sawtooth.