Re: DDS question: why sine lookup?

On Tue, 6 May 2025 16:46:16 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

On 2025-05-06 15:00, Jeroen Belleman wrote:

On 5/6/25 17:48, john larkin wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.
>
But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?
>
The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we'll average a
lot of steps and forget the big sawtooth reset. [...]

 
Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won't have a zero response
for all possible frequencies.
 
Second, the usual reconstruction filters do *not* interpolate
into straight lines.
 
Beyond that, I would have to think this over a bit more.
 
Jeroen Belleman
 
 
 

>
You don't want to use a sawtooth if you can help it, because it has huge
contributions from all harmonic orders.  It also puts a lot of demands
on the slew rate and settling of the DAC and any amplifiers used in the
filtering.  Errors there are of course nonlinear, because once an amp is
in slew limiting, it stops responding to its inputs for a bit.
>
It also emphasizes the close-in spurs.  Say you have two N-bit DDSes
running at the same average frequency but different phases.  The DAC
samples only the M high-order bits. It happens that at time t=0 the
accumulator overflows on the same clock cycle on both.
>
This will continue to happen until one of them overflows a cycle early
because the bottom N-M bits rolled over.
>
The resulting voltage difference between them is a full-scale,
one-clock-wide pulse, followed by a noisy baseline as the bottom N-M
bits roll over into the DAC's LSB at different times.  This will repeat
every cycle until the other DDS catches up.  This scenario will play out
some number of times in a full period, i.e. the least common multiple of
the accumulator size and the increment in clocks.
>
The energy in that glitch is much larger than in the noisy baseline, and
its timing is variable in complicated ways.
>
A triangle would be better, and of course that could be done pretty
simply, e.g. with a flip flop controlling a bunch of XOR gates, if you
don't mind halving the frequency.
>
Once you have a lookup table, a sine is as easy as anything else, and
minimizes the demands on the DAC, filters and amplifiers.
>
Cheers
>
Phil Hobbs

I'm Spicing things and what I'm seeing in the FFT of my DAC output,
with the sawtooth, is giant subharmonics at some magic frequencies.
Those contribute the most period jitter.

May as well use a sine, I guess. Still, my sim tools are useful in
tweaking the detais: NCO clock rate, lookup table size, DAC bits,
filter order. I have several products in design that need DDS clocks,
so some time playing with this is worth it. And it's interesting.

My Basic program generates a PWL file, given choices of clock rates,
bits, and waveform. I can import that to LT Spice and take over with
filtering and such. If I just output the obvious steps to the PWL
file, Spice will draw straight lines between points and it looks
awful. I want DAC steps. The fix is to output each point twice,
suitably spaced.

My FPGA guys say that an Efinix T55 can run a 48-bit phase accumulator
at 280 MHz. Yikes. One $10 T20 could make a dozen DDS's.