Re: DDS question: why sine lookup?

On 7/05/2025 11:32 pm, john larkin wrote:

On Wed, 7 May 2025 11:44:23 +0200, Arie de Muijnck <noreply@ademu.nl>
wrote:
 

On 2025-05-07 00:50, john larkin wrote:

On Tue, 6 May 2025 16:46:16 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:
>

On 2025-05-06 15:00, Jeroen Belleman wrote:

On 5/6/25 17:48, john larkin wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.
>
But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?
>
The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we'll average a
lot of steps and forget the big sawtooth reset. [...]

>
Two things are immediately obvious: First, the sawtooth will have
a variable frequency, and the filter won't have a zero response
for all possible frequencies.
>
Second, the usual reconstruction filters do *not* interpolate
into straight lines.
>
Beyond that, I would have to think this over a bit more.
>
Jeroen Belleman
>
>
>

>
You don't want to use a sawtooth if you can help it, because it has huge
contributions from all harmonic orders.  It also puts a lot of demands
on the slew rate and settling of the DAC and any amplifiers used in the
filtering.  Errors there are of course nonlinear, because once an amp is
in slew limiting, it stops responding to its inputs for a bit.

>
I was thinking that my DAC is just 5 or 6 resistors hanging off some
FPGA pins, and that drives a 3rd order (CLC) LC filter and the
comparator. So no opamps.
>
>
>

>
It also emphasizes the close-in spurs.  Say you have two N-bit DDSes
running at the same average frequency but different phases.  The DAC
samples only the M high-order bits. It happens that at time t=0 the
accumulator overflows on the same clock cycle on both.
>
This will continue to happen until one of them overflows a cycle early
because the bottom N-M bits rolled over.
>
The resulting voltage difference between them is a full-scale,
one-clock-wide pulse, followed by a noisy baseline as the bottom N-M
bits roll over into the DAC's LSB at different times.  This will repeat
every cycle until the other DDS catches up.  This scenario will play out
some number of times in a full period, i.e. the least common multiple of
the accumulator size and the increment in clocks.
>
The energy in that glitch is much larger than in the noisy baseline, and
its timing is variable in complicated ways.
>
A triangle would be better, and of course that could be done pretty
simply, e.g. with a flip flop controlling a bunch of XOR gates, if you
don't mind halving the frequency.
>
Once you have a lookup table, a sine is as easy as anything else, and
minimizes the demands on the DAC, filters and amplifiers.
>
Cheers
>
Phil Hobbs

>
If I'm using, say, 8 MS phase accumulator bits and a 5-bit DAC and
synthesizing one octave of frequency, the sine table is no big deal.
256 bytes of RAM per DDS unfolded.
>
I've been playing with sims. The sawtooth works OK but may be too
cute. I'll compare it to sines.
>
The pseudo-DAC output is always positive. It can go into one
comparator input and I can RC lowpass filter same into the other, to
switch on the waveform midpoint.
>
I reall need to get my FPGA kids to run the phase accumulator at 160
MHz. Run way below Nyquist.
>

>
>
Can't you fold the LIN to SIN conversion in the resistor values?

 I don't know.

You really ought to find out. Hanging resistors on successive taps of a shift register creates a Finite Impulse Response Filter. You have to taper the resistor values with a Hamming window to avoid Gibbs oscillations - I found out about that the hard way, but it isn't difficult.
You can certainly use one to convert a square wave into a pretty good approximation to a sine wave.
It doesn't lend itself to non-integer frequency division.

I can buy a small cheap R-2R resistor network, and a 8-8
bit sine lookup is easy in an FPGA.

I ended up having to use 10ppm 0.1% E96 resistors, and the more critical to get each resistance sufficiently correct, but I used a fairly long shift register. I was quite fond of the female bat acoustician I put the gear together for, and went in for a bit of over-kill.

Resistors are linear and sine is nonlinear.

Not a relevant point.
--
Bill Sloman, Sydney