Re: DDS question: why sine lookup?

On Tue, 06 May 2025 08:48:29 -0700, john larkin <jl@glen--canyon.com>
wrote:

A DDS clock generator uses an NCO (a phase accumulator) and takes some
number of MSBs, maps through a sine lookup table, drives a DAC and a
lowpass filter and finally a comparator. The DAC output gets pretty
ratty near Nyquist, and the filter smooths out and interpolates the
steps and reduces jitter.
>
But why do the sine lookup? Why not use the phase accumulator MSBs
directly and get a sawtooth, and filter that?
>
The lowpass filter looks backwards in time for a bunch of ugly samples
to average into a straight line. The older sine samples are the wrong
polarity! If the filter impulse response is basically zero over the
period of the sawtooth, and we compare near the peak, we'll average a
lot of steps and forget the big sawtooth reset.
>
I want to make four programmable clocks and don't want to buy DDS
chips. So use a cheap FPGA and a few resistors as the DAC. Synthesize
one octave and divide down for lower frequencies. Gotta sim that.
>
LT Spice really sucks with digital stuff. Building a phase accumulator
would be a horror. I'm working on a PowerBasic program that can dump
waveforms to a PWL file that LT Spice can import and filter. Qspice
would be better but I'd have to learn that and hack the phase
accumulator in c.
>
>

How about this?

https://www.dropbox.com/scl/fi/wefcwnm5zo70agmbsu88l/FPGA_DDS.jpg?rlkey=smexzxzd1j8o91752tw59jdas&raw=1

I only need to synthesize one octave, so I really want a bandpass
filter to chop out all the low frequency crud, especially junk from
the 3.3v supply.

R1C1 sets the comparator threshold to be the midpoint of the sine
wave. If its time constant is short, it provides some useful bandpass
effect too.

I can use a 3-pole filter in apps where a little jitter is OK.