Re: D correctly simulated by H never halts

On 5/29/2024 6:34 AM, olcott wrote:

On 5/28/2024 11:54 PM, Chris M. Thomasson wrote:

On 5/28/2024 8:29 PM, olcott wrote:

On 5/28/2024 10:05 PM, Chris M. Thomasson wrote:

[...]

too vague? Oh that is rich.

>
I had to start specifying the x86 language because dozens of reviewers
believed that D correctly simulated by H was supposed to report on the
behavior of non-input: int main() { D(D); }
>
It was only that I could show that this would require simulating
the x86 instructions of D incorrectly or in the wrong order that
I could prove that they were wrong. Their mistake was my primary
rebuttal for two years.
>

>
How do you simulate cmpxchg8b?

 That is not an x86 instruction it is an x64 instruction
https://phoenixnap.com/kb/x64-vs-x86
 https://www.felixcloutier.com/x86/cmpxchg8b:cmpxchg16b
 

Why do you say that its an x64 instruction? cmpxchg8b is on IA-32. I used it all the time back in the day. Here is some of my old assembly code for a DWCAS. By the way, DWCAS means double-width compare-and-swap:
https://web.archive.org/web/20060214112539/http://appcore.home.comcast.net/appcore/src/cpu/i686/ac_i686_masm_asm.html
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align 16
np_ac_i686_atomic_dwcas_fence PROC
   push esi
   push ebx
   mov esi, [esp + 16]
   mov eax, [esi]
   mov edx, [esi + 4]
   mov esi, [esp + 20]
   mov ebx, [esi]
   mov ecx, [esi + 4]
   mov esi, [esp + 12]
   lock cmpxchg8b qword ptr [esi]
   jne np_ac_i686_atomic_dwcas_fence_fail
   xor eax, eax
   pop ebx
   pop esi
   ret
np_ac_i686_atomic_dwcas_fence_fail:
   mov esi, [esp + 16]
   mov [esi + 0],  eax;
   mov [esi + 4],  edx;
   mov eax, 1
   pop ebx
   pop esi
   ret
np_ac_i686_atomic_dwcas_fence ENDP
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It's prototype is:
http://appcore.home.comcast.net/appcore/include/cpu/i686/ac_i686_h.html
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AC_SYS_APIEXPORT
int AC_CDECL
np_ac_i686_atomic_dwcas_fence
( void*,
   void*,
   const void* );
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