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On Fri, 28 Mar 2025 03:26:26 +0100I have not programmed SPARC either, but I would not consider branch delay slots to be a distinguishing feature - delay slots were a common feature in many (but not all) RISC architectures - most notably, IMHO, MIPS.
Janis Papanagnou <janis_papanagnou+ng@hotmail.com> wrote:
On 28.03.2025 03:03, Chris M. Thomasson wrote:You didn't ever programmed in SPARC asm. Your reading of SPARCOn 3/27/2025 6:59 PM, Janis Papanagnou wrote:>>>
But there were ideas! But not only the interesting ideas (like the
frame shift on the stack [SPARC]; one detail I memorized)
It's been a while since I coded up raw SPARC ASM. Remember that
branch delay slot? Ever use it with a MEMBAR instruction? Shit
would hit the fan.
As mentioned somewhere upthread I haven't ever programmed a SPARC on
assembler level, just studied some documents. I'm not even sure the
term "frame shift on the stack" that I used is accurate or correct;
it's just an informal description of a technical detail that I had
considered to be interesting. (Instead of copying parameters/results
with function calls between callers and callee you could just shift
a "stack window" by adjusting a register (or so).
>
So, no, I cannot remember a "branch delay slot". - Sorry. - Want to
elaborate on the story?
>
Janis
>
documents was so shallow that you didn't pay attention to highly
visible distinguishing feature as branch delay slot.
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