Re: [OT] SPARC (was Re: The integral type 'byte')

On 28/03/2025 14:20, Janis Papanagnou wrote:

On 28.03.2025 13:56, Michael S wrote:

On Fri, 28 Mar 2025 13:20:35 +0100
Janis Papanagnou <janis_papanagnou+ng@hotmail.com> wrote:

>
Just to understand; do you consider the 68k to be an "8-bitter"?

>
No, 68K was sold as "16-bit", but by modern use of the terms it is
32-bit CPU.

 

I have no idea how it was marketed, but I have always considered the 68k as a 32-bit architecture.  The 68000 had a 16-bit ALU and 16-bit databus, but its GPR's and address registers were 32-bit, and most instructions handled up to 32-bit data.  The 68020 had a 32-bit ALU and 32-bit buses, and was 32-bit by most measurements (there being no standard as to what "N-bit cpu" actually means).  To my mind, since the 68000 and 68020 had the same ISA, it makes no sense to say that one of these was 16-bit and the other 32-bit.
Marketing folks, of course, have other ideas!
(The 68k device I used most was the 68332 microcontroller, whose cpu core was a modified 68020 core.  I also used a few Coldfires later on.)

Thanks for clarifying.
 IIRC, I was certainly addressing and manipulating 8, 16, and 32 bit
entities with it. But it annoyed me to have a restriction that some
data manipulations required a 2-byte (or 4-byte?) alignment of data
(as far as memory serves). - Probably justifiable with it being a
"16-bitter". - Ah, well, anyway, never mind.
 

Natural alignment of data, up to the size of the normal accesses for the chip, has always seemed entirely natural to me.  I can't tell you if the 68k device I used - the 68332 - could or could not handle misaligned accesses, because it's not something I would normally do.