Re: [OT] SPARC (was Re: The integral type 'byte')

On 3/28/2025 7:33 AM, David Brown wrote:

On 28/03/2025 13:20, Michael S wrote:

On Fri, 28 Mar 2025 13:08:14 +0100
David Brown <david.brown@hesbynett.no> wrote:
>

On 28/03/2025 11:26, Michael S wrote:

On Fri, 28 Mar 2025 03:26:26 +0100
Janis Papanagnou <janis_papanagnou+ng@hotmail.com> wrote:

On 28.03.2025 03:03, Chris M. Thomasson wrote:

On 3/27/2025 6:59 PM, Janis Papanagnou wrote:

>
But there were ideas! But not only the interesting ideas (like
the frame shift on the stack [SPARC]; one detail I memorized)

>
It's been a while since I coded up raw SPARC ASM. Remember that
branch delay slot? Ever use it with a MEMBAR instruction? Shit
would hit the fan.

>
As mentioned somewhere upthread I haven't ever programmed a SPARC
on assembler level, just studied some documents. I'm not even sure
the term "frame shift on the stack" that I used is accurate or
correct; it's just an informal description of a technical detail
that I had considered to be interesting. (Instead of copying
parameters/results with function calls between callers and callee
you could just shift a "stack window" by adjusting a register (or
so).
>
So, no, I cannot remember a "branch delay slot". - Sorry. - Want to
elaborate on the story?
>
Janis

>
You didn't ever programmed in SPARC asm. Your reading of SPARC
documents was so shallow that you didn't pay attention to highly
visible distinguishing feature as branch delay slot.

>
I have not programmed SPARC either, but I would not consider branch
delay slots to be a distinguishing feature - delay slots were a
common feature in many (but not all) RISC architectures - most
notably, IMHO, MIPS.
>
The register window concept, however, was a lot less common (though
not unique to the SPARC), and much more relevant to the way you work
with the processor.
>

>
Register Window is a major part of Berkeley tradition. The processor
with Register Window that was sold and highest quantities is probably
not SPARC, but Intel i960. Another examples are AMD 29K and Intel
Itanium.

 I did not know that the Itanium had a register window - I did know about the AMD 29K.  It surprises me to hear that the i960 was sold in higher quantities than the SPARC, but since I have no real idea of the sales figures of either, I will take your word for it.
 

>
As to importance for asm coder, branch delay slot is more important
(i.e. more annoying) than register window, simply because in typical
program one has more branches than function calls.

 I would disagree.  Neither feature is particularly relevant if you are doing user-level programming in a high-level language.  In assembly, you have no choice but to understand and use the register window feature - it's a major part of coding.  The branch delay slot, on the other hand, can be ignored by simply using a NOP, for a slight efficiency cost. 

I also remember reading in some SPARC manual about using NOP's in branch delay slots. Programming the SPARC was really "fun" when it was in RMO mode... :^)

I vaguely recall the MIPS assembler handling delay slots somewhat automatically, but my experience using that was /very/ brief.  Make the most of the delay slot for optimal efficiency would, I expect, be annoying - but so is a lot of assembly coding for RISC devices!
 

At system programming level register window can be more important, in a
bad way.
At the level of programming in C, esp. for application programs, both
register windows and branch delay slots are transparent.
>

 Yes.
 Any classification of "distinguishing features" or "important features" is going to be quite subjective - it depends which other cpus you are comparing to.