Re: [OT] SPARC (was Re: The integral type 'byte')

On 2025-03-28, David Brown <david.brown@hesbynett.no> wrote:

On 28/03/2025 11:26, Michael S wrote:

On Fri, 28 Mar 2025 03:26:26 +0100
Janis Papanagnou <janis_papanagnou+ng@hotmail.com> wrote:
 

On 28.03.2025 03:03, Chris M. Thomasson wrote:

On 3/27/2025 6:59 PM, Janis Papanagnou wrote:

>
But there were ideas! But not only the interesting ideas (like the
frame shift on the stack [SPARC]; one detail I memorized)

>
It's been a while since I coded up raw SPARC ASM. Remember that
branch delay slot? Ever use it with a MEMBAR instruction? Shit
would hit the fan.

>
As mentioned somewhere upthread I haven't ever programmed a SPARC on
assembler level, just studied some documents. I'm not even sure the
term "frame shift on the stack" that I used is accurate or correct;
it's just an informal description of a technical detail that I had
considered to be interesting. (Instead of copying parameters/results
with function calls between callers and callee you could just shift
a "stack window" by adjusting a register (or so).
>
So, no, I cannot remember a "branch delay slot". - Sorry. - Want to
elaborate on the story?
>
Janis
>

 
You didn't ever programmed in SPARC asm. Your reading of SPARC
documents was so shallow that you didn't pay attention to highly
visible distinguishing feature as branch delay slot.

>
I have not programmed SPARC either, but I would not consider branch
delay slots to be a distinguishing feature - delay slots were a common
feature in many (but not all) RISC architectures - most notably, IMHO, MIPS.

I believe it was common for assemblers to hide branch delay slots from
the programmer by inserting the no-op instructions into them
automatically, so you wouldn't have to think about them, unless you
wanted to take advantage of them.

I don't remember the details. I seem to recall that one way of doing it
is to have a different mnemonic for a branch pseudo-instruction which
inserts the no-op into the following delay slot, versus a mnemonic
that gives you the raw instruction, following which you have to put
something into the delay slot yourself.

I also seem to recall that at least one of the mainstrema RISC families
made the mistake of varying the number of branch delay slots across
family members (as the pipelines got deeper), so that code for an older
chip wouldn't run due to not having enough instructions in the delay
slot.

Janis could have easily worked in assembly on a processor without
being aware of branch delay slots.


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