Re: Top 10 most common hard skills listed on resumes...

On 08/09/2024 23:34, Waldek Hebisch wrote:

David Brown <david.brown@hesbynett.no> wrote:

>
And while microcontrollers sometimes have a limited form of branch
prediction (such as prefetching the target from cache), the more
numerous and smaller devices don't even have instruction caches.
Certainly none of them have register renaming or speculative execution.

 IIUC STM4 series has cache, and some of them are not so big.  There
are now several chinese variants of STM32F103 and some of them have
caches (some very small like 32 words, IIRC one has 8 words and it
is hard to decide if this very small cache or big prefetch buffer).

There are different kinds of cache here.  Some of the Cortex-M cores have optional caches (i.e., the microcontroller manufacturer can choose to have them or not).
<https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization>
Flash memory, flash controller peripherals, external memory interfaces (including things like QSPI) are all specific to the manufacturer, rather than part of the Cortex M cores from ARM.  Manufacturers can do whatever they want there.
So a "cache" of 32 words is going to be part of the flash interface, not a cpu cache (which are typically 16KB - 64KB, and only found on bigger microcontrollers with speeds of perhaps 120 MHz or above).  And yes, it is often fair to call these flash caches "prefetch buffers" or read-ahead buffers.  (You also sometimes see small caches for external ram or dram interfaces.)

A notable example is MH32F103.  Base model officially has 64kB RAM and
256KB flash.  AFAIK this flash is rather slow SPI flash.  It also
has 16kB cache which probably is 4-way set associative with few
extra lines (probably 4) to increase apparent associativity.
I write probably because this is result of reasoning based on
several time measurements.  If you hit cache it runs nicely at
216 MHz.  Cache miss costs around 100 clocks (varies depending on
exact setting of timing parameters and form of access).
 Similar technology seem to be popular among chines chip makers,
especially for "bigger" chips.  But IIUC GD use is for chips
of size of STM32F103C8T6.