Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers

Sujet : Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers
De : buzz_mccool (at) *nospam* yahoo.com (Buzz McCool)
Groupes : comp.lang.vhdl comp.arch.fpga comp.arch.embedded
Date : 01. Aug 2024, 21:17:32

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Organisation : A noiseless patient Spider
Message-ID : <v8gn0c$2b8r9$1@dont-email.me>
References : 1 2
User-Agent : Mozilla Thunderbird

On 7/21/2024 9:16 AM, Nioclás Pól Caileán de Ghloucester wrote:

I found that the overwhelming majority of the Internet's solution to slowing down a fast clock (for making the pulsing of an LED visible to the human eye) was either using vendor-specific, proprietary clock managers and PLLs or implementing some twenty-something-bit-wide counter as to count hundreds of thousands of clock cycles and generate a 1 Hz output.

If you did not have access to FPGA shift register primitives, what would be the most efficient way to build a prescaler from discrete parts?

Date	Sujet	#	Auteur
21 Jul 24	Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers	5	Nioclás Pól Caileán de Ghloucester
1 Aug 24	Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers	2	Buzz McCool
7 Aug 24	Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers	1	Fereydoun Memarzanjany
7 Aug 24	Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers	2	Fereydoun Memarzanjany
7 Aug 24	Re: A Simple VHDL Abstraction of an Efficient Clock Prescaler Using Cascading Shift Registers	1	Nioclás Pól Caileán de Ghloucester

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