Re: New Pico2

On Tue, 2024-08-13 at 08:40 +0100, Richard Kettlewell wrote:

druck <news@druck.org.uk> writes:

On 11/08/2024 22:32, Single Stage to Orbit wrote:

I've got a RISCV baremetal operating system I might bring up on
this device but looking at the datasheet for the RISCV processor
used, it's only got machine mode and user mode, no supervisor
mode and no paging. It does not even support any of the Sv
pagetables so that's a challenge.

 
Also no floating point, if I’ve understood correctly?
 

I just had to re-check the datasheet and you're right, the Hazard3
cores do not handle floating point. That's deeply disappointing.

The M33 cores do support single and double precision floating point,
single floating point within the M33 cores and double precision maths
using one of its three coprocessors (gpio, maths and the other I
forget). I guess we could just ring the doorbell to get the ARM core to
do the maths for the Hazard3 core. :-D

The joys open "open source" CPUs with no standardised feature sets.
 

Most interestingly enough, you can actually boot up with one
RISCV core and one ARM core, two RISCV cores or both ARM cores.
Mixed processor cores that'll be fun to see what we can do with
that.

 
I think they did that for all the people who keep insisting they
should move to the "new future" of RISC V. Now they can find out
how badly it compares to a contemporary ARM core.

 
It’s a slightly odd device, isn’t it?
 
If you wanted to explore RISC-V then there’s more flexible options.
If you just wanted a microcontroller for something and didn’t care
too much about CPU architecture then the dual-architecture thing is
wasted. Two entire CPU cores that you don’t get to use.

Yes the datasheet says the unused cores are gated off.
--
Tactical Nuclear Kittens