Sujet : Re: OT: horrible 8086 segmentation
De : ldo (at) *nospam* nz.invalid (Lawrence D'Oliveiro)
Groupes : comp.sys.raspberry-piDate : 23. Dec 2024, 23:55:52
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vkcppo$1dp54$6@dont-email.me>
References : 1 2 3 4 5 6 7
User-Agent : Pan/0.161 (Chasiv Yar; )
On Mon, 23 Dec 2024 03:26:11 +0000, Brian Gregory wrote:
On 18/12/2024 06:22, Lawrence D'Oliveiro wrote:
>
On Sun, 01 Dec 2024 15:11:05 +0000, Richard Kettlewell wrote:
The Natural Philosopher <tnp@invalid.invalid> writes:
>
I also remember a zilog Z8000?
>
Yes, although also with a segmented memory model.
Its segmentation scheme made Intel x86 look good.
Not that unusual. Compare to some of the Microchip PICs. Some have
really bizarre bank switching arrangements and so on.
I think the Apple II RAM expansion card worked by switching to a different
bank (48K each?) every time a particular control register byte was
written. You couldn’t just write a bank number: instead, you had to repeat
the write N number of times, and I guess remember where you started from,
to get to the right bank.
But this was because the CPU itself only supported 16-bit addressing. What
was Zilog’s excuse?