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On 2/22/25 11:52 AM, olcott wrote:*Correct simulation means emulates the machine code as specified*On 2/22/2025 5:05 AM, joes wrote:Only because that statement is based on a false premise.Am Thu, 20 Feb 2025 18:25:27 -0600 schrieb olcott:>On 2/20/2025 4:38 PM, Alan Mackenzie wrote:Honestly, you're gonna die first, one way or the other.olcott <polcott333@gmail.com> wrote:As soon as people fully address rather than endlessly dodge my keyOn 2/20/2025 2:38 AM, Mikko wrote:>On 2025-02-20 00:31:33 +0000, olcott said:Yes. It would be a relief if you could move on to posting somethingEvery post that I have been talking about for two or more years hasI have given everyone here all of the complete source code for a fewTrue but irrelevant. OP did not specify that HHH means that
years
particular code.
referred to variations of that same code.
new and fresh.
points I will be done.
>Let's start with a root point.Since DD halts, that's dead in the water.
All of the other points validate this root point.
*Simulating termination analyzer HHH correctly determines*
*the non-halt status of DD*
>
Despicably intentionally dishonest attempts at the straw-man
deception aside:
>
DD correctly simulated by HHH cannot possibly terminate
normally by reaching its own "return" instruction.
>
Since HHH doesn't correctly simulate its input, your statement is just a fabrication of your imagination.
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