Sujet : Re: DDS, again
De : jl (at) *nospam* glen--canyon.com (john larkin)
Groupes : sci.electronics.designDate : 11. Dec 2024, 19:50:00
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <0bnjljpmode5sgjeun99nonvvmosd7bvt0@4ax.com>
References : 1
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On Tue, 10 Dec 2024 18:38:18 -0800, john larkin <
JL@gct.com> wrote:
I have been unsuccessful in getting LT Spice to simulate a DDS
frequency generator. It's bad enough trying to make the NCO part, but
whenever I get close it stalls or throws convergence errors.
>
So I wrote a PowerBasic program that's the 32-bit NCO... GC_Num.exe.
>
Making a proper .WAV file would be a nightmare, so it outputs as a
text file with just time data per line, where data is the
selected number of MS bits of the phase accumulator.
>
LT Spice can read the file, and then do whatever it wants: sine, DAC,
filter, comparator, FFTs.
>
https://www.dropbox.com/scl/fo/o0mdxxqvxupg6ynz7i7rx/AMPMbv9NOY4mJFXggTGUqJ8?rlkey=9ecl38npbgy8kxuzd9bako4kr&dl=0
>
Spice reads the file as a piecewise-linear thing, so wrecks the nice
MSB data steps. I had to fool it by outputting each clocked phase
accumulator value twice, as
>
bits time
bits time+0.9*clock_period
>
same data bits both lines. Looks pretty steppy.
Given a 40 MHz phase accumulator, one could spin up a clock at some
mutiple, 160 MHz maybe, and fake the dac/lowpass/comparator thing to
reduce jitter.
I think it's just a lookup table on some MSBs of the 40 MHz phase
accumulator. Of course the new fake DDS clock output would be
quantized to the 160 MHz clock domain. Maybe.